1. Field of the Invention
The present invention relates to display devices and more particularly to liquid crystal display devices.
2. Description of the Prior Art
The following are circuits representative of the prior art.
U. S. Pat. No. 3,872,360 to Dill et al. shows a drive system for a dynamic scattering liquid crystal display material which is driven by a D.C. signal applied via a capacitor. The capacitor is selected and periodically charged by a transistor. The patented drive system employs a D.C. voltage signal in the range of twenty to thirty volts to drive a dynamic scattering LCD, whereas the drive circuit according to the present invention employs an A.C. signal in the range of 1.5 volts rms to drive a twisted nematic liquid crystal display material. Dynamic scattering liquid crystal display material has yet to be proven to be reliable and the higher D.C. voltage imposes considerable stress and limitation on the drive circuits.
U.S. Pat. No. 4,239,346 to Lloyd described a fabrication technique for the drive system in U.S. Pat. No. 3,872,366 described above.
U.S. Pat. No. 4,094,582 to Goodman et al. describes a drive system for a LCD employing a single FET device per liquid crystal PEL. The device does not have memory and develops significant D.C. voltage across the liquid PEL. The lack of memory limits the system of the patent to relatively low density and/or very high refresh rates. Further, the development of the D.C. voltage across the liquid crystal PEL reduces reliability of the liquid crystal material. The drive system according to the present invention has built in memory and eliminates D.C. build up across the liquid crystal PEL.
U.S. Pat. No. 3,485,292 to Nonomura et al. describes a segmented liquid crystal display as opposed to a matrix LCD. As with U.S. Pat. No. 3,873,360 described above, the circuit includes a transistor plus a capacitor driving the LCD segment. As before, this system suffers from the yield and reliability disadvantages of the capacitor. The drive system according to the present invention has built in memory and does not require capacitors for storage of PEL drive data.
U.S. Pat. No. 4,103,297 to McGreivey et al. appears to be an improvement to U.S. Pat. Nos. 3,973,360 and 4,239,346 described above in which an ion implantation is used to create a light sensitive FET structure driving each individual PEL. However, the circuit still employs a transistor plus a capacitor with the disadvantages as described above.
IBM Technical Disclosure Bulletin Vol. 23, Number 6, November, 1980, at page 2557 describes a liquid crystal drive system requiring a capacitor and a resistor per picture element (PEL).
IBM Technical Disclosure Bulletin Vol. 24, Number 7B, December, 1981, page 3681 describes a A.C. drive system for a LCD requiring a capacitor for storage for each PEL.
Although the prior art shows a variety of techniques for driving liquid crystal display systems, none of the prior art identified above shows a drive system in which internal memory for each PEL driver eliminates the need for a separate memory device such as a capacitor.
In an article by DiMaria et al. in the IEEE Electron Devices Letters, Vol. EDL-1, Number 9, Page 1797; September, 1980, a dual electron injector structure is described which includes an electrically alterable memory employing a floating polycrystalline silicon storage layer and silicon rich SiO electron injectors. The article generally describes the electrically alterable memory using a dual electron injector structure. However, the article does not describe nor suggest the circuit structure employed in a preferred embodiment of the present invention.
U.S. Pat. No. 4,104,675 shows the the use of a graded band-gap structure of silicon enriched SiO.sub.2 between pure SiO.sub.2 and metal or silicon to significantly enhance the injection of either holes or electrons from conductor through the silicon enriched insulator. It is this concept which is used in the creation of the DEIS, the memory device described by DiMaria et al discussed above. The patent and the referenced article in no way suggest the LCD drive circuit of the present invention.
A paper presented at the 1981 IEEE International Solid States Circuit Conference at Page 38 of the proceedings thereof, describes a dual gate floating gate FET device which operates with a single polarity voltage and which has a writeerase operation independent of the field effect transistor action. The present invention incorporates a similar type of `dual gate` dual electron injection structure (DEIS) as described above into the PEL drive circuitry. The DEIS device function is to store the state of the PEL, ie. either selected or not selected. In the selected state, the DEIS device is conductive and the AC drive signal is imposed across the LC cell. On the other hand, when the DEIS device is programmed `off`, it is in its open ciruit condition and thereby isolates the AC signal from the LC PEL.
However, instead of utilizing the DEIS structure on single crystalline silicon as above, the present invention incorporates the dual gate DEIS structure on polysilicon. The processing techniques used to create the DEIS structure is consistent with the processing techniques used for making polysilicon FET devices for large area display devices. Specifically, there processes include low pressure chemical vapor depositions at relatively low temperatures (600 degrees C). The circuits, devices and processes are discussed in greater detail below.
The Paper `Polysilicon FET Devices for Large Area Input/Output Applications` by S. Depp, A. Juliana and B. Huth in the IEDM Technical Digest, pp 703-706, 1980, in addition to describing the FET device characteristics of polysilicon devices, also describes PEL circuit drive schemes for large area LCD's.
The PEL drive circuitry descibed in the Article also eliminates the capacitor as a memory element per PEL, being replaced by a memory circuit. The memory circuit is a classic latch or flip-flop. In one case, the circuit consists of 4 transistors and 2 polysilicon resistors and in the second case, a CMOS version, the resistors are replaced with active devices. The first version, somewhat simpler to fabricate, consumes DC power, the level a function of process capability. The second case, the CMOS latch dissipates no DC power but has a total of 6 active devices.
In summary, the PEL ciruits suggested by S. Depp et al. do have built-in memory which is considerably more complex than the present invention.